Computer systems and networks · GCSE Computer Science
The fetch–decode–execute cycle
GCSE Computer Science fetch–decode–execute: how the PC, MAR, MDR, CIR and ALU move one instruction from memory through the CPU, every cycle.
PC holds the next address. MAR gets that address. Memory fills the MDR. Instruction copies to the CIR. Decode, then the ALU (or memory) executes. PC already points at the next one.
The important bits
What you need to know
- 1
The fetch–decode–execute cycle is how a Von Neumann CPU runs a stored program: fetch an instruction from RAM, decode it, execute it, then repeat.
- 2
The program counter (PC) holds the address of the next instruction to fetch. At the start of a normal cycle it is copied to the memory address register.
- 3
The memory address register (MAR) holds the address being accessed on the address bus. Memory uses it to know which location to read or write.
- 4
The memory data register (MDR) holds the data or instruction just read from memory, or the data about to be written. It sits on the data bus side of the CPU.
- 5
The current instruction register (CIR, or IR) holds the fetched instruction while it is decoded. The control unit interprets the opcode and sends control signals.
- 6
The arithmetic logic unit (ALU) carries out arithmetic and logic during execute: add, subtract, compare, AND, OR, NOT, and similar operations your spec names.
- 7
After fetch, the PC is incremented so it already points at the next instruction. A jump or branch during execute overwrites the PC with a new address.
- 8
Buses: address bus carries the location (MAR), data bus carries the bits (MDR), control bus carries read/write and timing signals from the control unit.
Quotations worth analysing
Short evidence. Real method.
“The program counter holds the address of the next instruction to be fetched.”
Address, not the instruction itself. Students who say the PC “stores the instruction” have mixed it up with the CIR.
“Fetch, decode, execute.”
Three stages, in that order. Execute is not “the ALU always”; it might be a memory load, a store, or a jump that only updates the PC.
“The MAR is loaded from the PC; the instruction is then copied from the MDR to the CIR.”
That order is the method mark. Skipping the MDR or sending the PC onto the data bus loses the picture.
Go deeper
Fetch is an address, then a copy, then an increment
Start with a concrete PC, say 200. Copy 200 into the MAR. Send a read along the control bus. Memory location 200 places its bits on the data bus; they land in the MDR. Copy those bits into the CIR — that is the instruction, for example ADD 15. Increment the PC to 201 so the next cycle knows where to go unless execute changes it. Decode looks at the opcode in the CIR and decides what execute means. If it is ADD 15, the address 15 may go to the MAR, the value at 15 into the MDR, and the ALU adds it to the accumulator. If it is a jump to 240, execute writes 240 into the PC and the increment you already did is overwritten. Write that sequence as a numbered list in the exam; a paragraph that names the registers in the wrong order scores like a jumble.
Go deeper
Do not put RAM inside the ALU
The ALU does arithmetic and logic on values that have already been fetched. It does not store the program. RAM holds instructions and data; registers hold the tiny working set for this cycle; cache (if asked) sits between them as a faster copy. Students draw the ALU connected to the hard disk, or say the MDR “decodes”. Decoding is the control unit reading the CIR. The MDR is a parking bay for bits coming off or onto the data bus. When a question gives a list of registers, match each to one job: PC = next address, MAR = address on the bus, MDR = data on the bus, CIR = this instruction, accumulator (if named) = ALU result. One accurate sentence each beats a long mix-up. Clock speed then just means how many of these cycles you can start per second — until memory lag or a branch stalls the story.
See the idea in action
Instruction at address 50 is LOAD 8 (copy the value at memory 8 into the accumulator). Memory[8] holds 17. PC starts at 50. Fetch: PC → MAR (MAR = 50). Memory read. MDR = instruction LOAD 8. MDR → CIR. PC incremented to 51. Decode: Control unit reads CIR: opcode LOAD, operand address 8. Execute: MAR = 8. Memory read. MDR = 17. 17 copied to the accumulator. Next cycle will fetch from 51 because the PC was incremented and LOAD did not branch. If the instruction had been JUMP 90, execute would set PC = 90 and the following fetch would not use 51. That is the whole cycle with named registers, not a slogan.
Exam technique
Turn knowledge into marks
Learn one clean FDE description: PC holds next address → MAR → memory → MDR → CIR → decode in the control unit → execute in the ALU or as a memory/jump operation → PC already updated. If you mix RAM into the ALU you lose the picture.
Common mistakes
Do not give these marks away
- 01
Saying the program counter stores the instruction, or the CIR stores an address.
- 02
Skipping the MAR or MDR in a fetch description and jumping from PC to “the CPU gets the instruction”.
- 03
Writing that every execute stage is an ALU calculation, including loads, stores and jumps.
What is the role of the program counter in the fetch–decode–execute cycle?
ATo store the entire operating system
BTo hold the address of the next instruction to fetch
CTo draw graphics on the monitor
DTo encrypt files on the hard drive
Show the answer
To hold the address of the next instruction to fetch. Each cycle the CPU must know where the next instruction lives in memory. The PC stores that address and is updated as instructions run, including jumps. The CIR holds the instruction itself.
Quick questions
If this is the bit you searched
What happens in the fetch stage GCSE Computer Science?
The address in the PC is copied to the MAR, the instruction is read from memory into the MDR and then into the CIR, and the PC is incremented to the next instruction address.
What is the difference between the MAR and the MDR?
The MAR holds an address (where to read or write). The MDR holds the bits being transferred (an instruction or a data value). Address bus versus data bus.
What does the ALU do in execute?
It performs arithmetic and logic on values already in registers. Not every instruction uses the ALU; some only move data or change the PC.
Why is the PC incremented during fetch?
So the CPU is already aimed at the next instruction in sequence. A branch during execute can overwrite that address if the program must jump.